Hot-electron induced n-channel MOSFET degradation has become a serious concern in present and future VLSI circuits due to the ever-increasing channel electric field in scaled devices. Hot-carrier degradation effects are especially crucial to the reliability of those devices which rely on electrical charge transfer mechanisms such as avalanche injection, channel injection, Fowler-Nordheim tunnelling, hot-electron injection from the substrate, etc. Included in this category of devices are electrically programmable read-only memories (EPROMS) as well as electrically programmable and electrically erasable memories (EEPROMS).
Flash memories (e.g., EEPROMs) are especially sensitive to degradation effects due to the fact that there are a substantial number of hot-electrons generated in each cell during electrical programming and erasing. In these flash memories, hot-electron performance is pushed to extreme limits. For example, during flash memory cycling (i.e., when the device is repeatedly programmed and erased), a significant number of substrate hot-electrons are trapped within the insulating gate oxide layer separating the drain region from the floating gate. The greater the number of cycles that a flash memory device is subjected to, the greater the number of carriers that become trapped in the gate oxide.
Hot-electron degradation effects are often observed in flash memories in two ways. Most noticeably, the erase/programming times for a given memory array are increased far beyond their normal limits. This phenomena is frequently referred to as "erasetime/programtime push-out". This means that as the devices are repeatedly cycled, a greater amount of erase/program time must be allotted for each successive cycle in order to insure that the entire array is completely charged or discharged.
The second way that degradation effects are manifested in a flash memory array is in the form of an excess ("apparent") charge loss which renders the memory devices unreliable. That is, even though the device is initially programmed to an "apparently" correct level, with time that programming level may drop below the limits of reliable operation. This "apparent" charge loss is caused by a shift in the transconductance of the devices after extensive program/erase cycles.
Although the exact mechanism for device degradation is still not known, many studies have indicated that it could be due to hydrogen-related interface state generation. This theory suggests that hydrogen is incorporated into the device structure during various processing steps--including the final annealing step. One source of hydrogen that maybe introduced into the device is the hydrogen-rich passivation layer, which typically comprises some form of oxide or nitride (e.g., oxynitride is commonly used).
Many approaches have been suggested for improving the hot-electron stability in MOS devices. For example, one group of researchers have successfully modified the drain doping profile by grading the drain or employing light-doping levels for the purpose of reducing the channel electric field strength. However, even with the use of these field-reducing structures, hot-electron induced degradation may still persist.
In a paper disclosed in IEDM 88, beginning on page 22, entitled "Improvement of Endurance to Hot-Carrier Degradation by Hydrogen Blocking P-SiO" by S. Yoshida et al., the use of a plasma silicon oxide was proposed as a remedy to the hot-electron problem. The authors believed that a blocking effect against hydrogen may be created by trapping the hydrogen atoms with dangling bonds present in the plasma silicon oxide layer. The plasma silicon oxide was shown to have an excellent capability of trapping and blocking hydrogen.
An alternative technique of performing a final anneal in a nitrogen ambient, rather than in a normal hydrogen ambient, is disclosed in an article by F-C. Hsu et al. entitled "Effective Final Anneal on Hot-Electron Induced MOSFET Degradation", IEEE Electron Device Letters, Vol. EDL-6, No. 7, July, 1985. This article reports that hydrogen content in certain devices can be reduced by performing a final anneal in a nitrogen atmosphere. Thus, hot-electron degradation may be suppressed to a negligible level. A lower hydrogen content leads to lower degradation as reported by Hsu et al. These results strongly support the hydrogen model for hot-electron-induced device degradation.
Another technique which teaches using a long nitrogen anneal is disclosed in an article by Shuo-Tung Chang et al., entitled "Reduced Oxide Charge Trapping in Approved Hot-Electron Reliability and Submicrometer MOS Devices Fabricated by Titanium Salicide Process", IEEE Electron Devices Letters, Vol. 9, No. 5, May, 1988. The nitrogen anneal is discussed in connection with a titanium salicide (self-aligned silicide) process, which is a new technique to reduce source drain resistance in silicon gate devices. The titanium silicide forms the gate electrode of the device. The authors found that titanium sputtering can cause radiation damage at the silicon-oxide interface by generating interface states, thereby degrading transistor performance. Typically, a hydrogen anneal was performed to remove this radiation damage. The authors discovered that using a nitrogen, rather than a hydrogen, anneal results in lower hot-electron degradation.
Even with the use of some of these above mentioned techniques, hot-electron stress in flash memories remains a very serious problem; particularly where the flash memories are used in extended cycle applications. Here they must have the ability to cycle many times without suffering erasetime push-out or excessive charge trapping in the oxide layer.
As will be seen, the present invention provides a method of fabricating flash memory devices which includes depositing a barrier layer of titanium underlying and generally coincident with, normal metalization layers. This titanium barrier layer is not intentionally converted to silicide and actually forms part of the interconnect metalization material. The inclusion of this barrier layer acts to prevent hydrogen present in the passivation layer from interacting with the continuous charge transfer that occurs in the gate oxide region of the memory devices. Using the method of the present invention, the push-out of erasetimes becomes negligible while the reliability of the flash memory devices is substantially enhanced.